Recently, there have been developed television receivers having extended functions capable of displaying video images by various display forms on its display. Many of the functions are carried out using video memories. In the functions, there has been known a function for simultaneously displaying multiple channel images by reducing each on a smaller scale on one screen. This function is called the multi-image display function. This multi-image display function is useful, for instance, for checking programs being simultaneously broadcasted in various broadcast stations. Because a viewer can change to a view of his or her favorite channel program only from the multi-image display.
Referring now to FIG. 1, a conventional multi-image display system will be briefly described. FIG. 1 is a block diagram showing an example of the conventional multi-image display system.
In FIG. 1, television broadcast signals Rf are supplied from an input terminal 1 to a tuner 2. The input terminal 1 receives the television broadcast signals Rf through an antenna (not shown). The tuner 2 selects a desired channel program from the television broadcast signals Rf. The tuner 2 further demodulates a composite video signal Scv from the selected television broadcast signal Rf. The composite video signal Scv is supplied to a color signal decoder 3 and a sync separator 4.
The color signal decoder 3 decodes a luminance signal Y and two color difference signals B-Y and R-Y from the composite video signal. The luminance signal Y and the color difference signals B-Y and R-Y are applied to analog-to-digital converters (referred to as A/D converters hereafter) 5, 6 and 7, respectively. Then, outputs from the A/D converters 5, 6 and 7 are supplied to frame memories 9, 10 and 11, respectively.
The sync separator 4 separates a vertical sync signal Svs and a horizontal sync signal Shs from the composite video signal Scv. The vertical sync signal Svs and the horizontal sync signal Shs are supplied to an address generator 8. The address generator 8 generates write addresses for the frame memories 9, 10 and 11 based on the sync signals Svs and Shs. The address generator 8 further generates read addresses based on a read sync signal Srs supplied from a read sync signal generator 12. The read addresses are applied to the frame memories 9, 10 and 11 in a read operation for the frame memories 9, 10 and 11. Respective data read out from the frame memories 9, 10 and 11 are supplied to digital-to-analog converters (referred to as D/A converters hereafter) 14, 15 and 16. The D/A converters 14, 15 and 16 restore the digitalized signals of the luminance signal Y and the color difference signal B-Y and R-Y to their corresponding analog signals. The analog signals of the luminance signal Y and the color difference signal B-Y and R-Y are supplied to a display device (not shown) through output terminals 17, 18 and 19.
The address generator 8 sets up a prescribed number of address areas, e.g., sixteen areas a1 to a16, as shown in FIG. 2, in each of the frame memories 9, 10 and 11. The address areas a1 to a16 are designated to sixteen television channels, e.g., channels Ch1 to Ch16 in the order. For example, the address area a2 is mapped to a section having horizontal addresses "256" to "511" and vertical addresses "64" to "127". In total, each frame memories 9, 10 and 11 has the address space having horizontal addresses "0" to "1023" and vertical addresses "0" to "255". Thus, the luminance signal Y and the color difference signal B-Y and R-Y of each channels Ch1 to Ch16 are stored in their designated address areas a1 to a16, respectively.
The color singals Y, B-Y, R-Y stored in the frame memories 9, 10 and 11 have been thinned out to 1/16 times in the writing operation by controlling the write addresses.
When the stored data of the frame memories 9, 10 and 11 are read out, a displayed image, as shown in FIG. 3, is obtained on a screen S of the display device. In FIG. 3, image areas p1 to p16 correspond to the address areas a1 to a16 of the frame memories 9, 10 and 11. Numerals "0", "256", "512" and "768" along the horizontal direction and numerals "0", "64", "128" and "192" along the horizontal direction indicate bias values, as described later.
The multi-image display system of FIG. 1 further includes an automatic channel changer 13. The automatic channel changer 13 generates a channel sweep signal Scs in the multi-image display operation. The channel sweep signal Scs is applied to the tuner 2 so that the composite video signals Scv of each channels Ch1 to Ch16 are successively output from the tuner 2. The channel sweep signal Scs is also applied to the address generator 8. Thus, the address generator 8 successively generates prescribed write addresses in response to the channels Ch1 to Ch16. The channel sweep operation carried out in the automatic channel changer 13 is not illustrated but may be controlled by a system control circuit, such as a microcomputer.
Referring now to FIGS. 4 and 5, an example of the address generator 8 will be described. FIG. 4 is a block diagram showing a detailed circuit of the address generator 8. FIG. 5 is a graph-chart showing the horizontal sync signal Shs and its related signals, as described later.
In FIG. 4, the address generator 8 has two input terminals 21 and 27. These input terminals 21 and 27 are provided for receiving the horizontal and the vertical sync signals Shs and Svs from the sync separator 4 (see FIG. 1).
The horizontal sync signal Shs is placed in a horizontal blanking period between two successive video image signals Svi, as shown by a graph Scv in FIG. 5. The horizontal blanking period comprises a leading blanking period TY in the front of a video image period TX and a following blanking period TZ in the rear of a preceding video image period TX. The graph Scv in FIG. 5 presents the composite video signal Scv. The video signals Svi occur in every horizontal scanning periods TS of the composite video signals Scv. The horizontal sync signal Shs is applied to a horizontal wave shaping circuit 22. The horizontal wave shaping circuit 22 shapes the horizontal sync signal Shs into a signal, as shown by a graph Shs' in FIG. 5. The signal Shs' is further shaped to a pulse signal, as shown by a graph Phs in FIG. 5.
The pulse signal (referred to as horizontal sync pulse hereafter) Phs is supplied to a horizontal counter 20. The horizontal sync pulse Phs resets the horizontal counter 23. The horizontal counter 23 starts a count operation of prescribed clock signals in every reset by the horizontal sync pulse Phs. Thus, the horizontal counter 23 generates horizontal addresses AH as its count data.
The horizontal addresses AH are supplied to a first bit shift circuit 24. The first bit shift circuit 24 thins out the horizontal addresses AH to 1/4 times. This thinning operation is achieved by shifting the horizontal addresses AH by two bits. As a result, a thinned horizontal addresses AHt with values "0" to "255" are output while the horizontal addresses AH with values, e.g., "0" to "1023". The thined horizontal addresses AHt are supplied to a first adder 25. The first adder 25 is further coupled to a horizontal bias generator 34.
The first adder 25 adds a prescribed bias value Bh supplied from the horizontal bias generator 34 to the thinned horizontal addresses AHt. Thus, biased horizontal addresses AHb is obtained from the first adder 25. The biased horizontal addresses AHb are supplied to the frame memories 9, 10 and 11 (see FIG. 1) through a horizontal address output terminal 26.
Similar operations are carried out for obtaining biased vertical addresses AVb through a circuit coupled to the input terminal 27.
The vertical sync signal Svs is placed in a vertical blanking period of the composite video signal Scv. The vertical sync signal Svs is applied to a vertical wave shaping circuit 28. The vertical wave shaping circuit 28 shapes the vertical sync signal Svs into a pulse signal Pvs.
The pulse signal (referred to as vertical sync pulse hereafter) Pvs is supplied to a vertical counter 29. The vertical sync pulse Pvs resets the vertical counter 29. The vertical counter 29 starts a count operation of prescribed clock signals in every reset by the vertical sync pulse Pvs. Thus, the vertical counter 29 generates vertical addresses AV as its count data.
The vertical addresses AV are supplied to a second bit shift circuit 30. The second bit shift circuit 30 thins out the vertical addresses AV to 1/4 times. This thinning operation is achieved by shifting the vertical addresses AV by two bits. As a result, a thinned vertical addresses AVt with values "0" to "63" are output while the vertical addresses AV with values, e.g., "0" to "255". The thined vertical addresses AVt are supplied to a second adder 31. The second adder 31 is further coupled to a vertical bias generator 35.
The second adder 31 adds a prescribed bias value Bv supplied from the vertical bias generator 35 to the thined vertical addresses AV'. Thus, biased vertical addresses AVb is obtained from the second adder 31. The biased vertical addresses AVb are supplied to the frame memories 9, 10 and 11 (see FIG. 1) through a vertical address output terminal 32.
The bias values Bh and Bv are decided for every image area p1 to p16, as shown in FIG. 3, on the screen S of the display device. For instance, the bias values Bh and Bv for the image area p2 are given values of "256" and "0", respectively. When the selected channel is shifted according to the channel sweep operation, the current channel is displayed on the following image area p3. The bias values Bh and Bv corresponding to the image areas p3 are given values of "512" and "0", respectively. In similar manner, the bias values Bh and Bv corresponding to the image areas p16 are given values of "768" and "192", respectively.
According to the conventional address control circuit for video memories of multi-image display systems, each of the frame memories 9, 10 and 11 stores the data extending in both the entire horizontal scanning period period TS (see FIG. 5) and the entire vertical scanning period period. When the stored data are read out, the image of the multi-image display operation includes horizontal and vertical blanking periods, as shown by hatching line areas in FIG. 6. These areas corresponding to the horizontal and vertical blanking periods make the image shabby. In addition, a portion of each frame memory is fruitlessly used for the data of the blanking periods. In other words, the conventional address control circuit for video memories of multi-image display systems conventional requires memories with relatively large memory capacities.